High performance programmable clock integrated circuits (ICs) can require precise control of active and passive components on chip to accurately define the design parameters. However, IC fabrication processes can introduce uncontrollable variations in such on-chip active and passive components. Conventionally, post fabrication steps, such as trimming, are used to finely tune circuit components to arrive at a desired performance. A drawback to such conventional approaches can be the additional post-fabrication steps, including additional test time, and/or complex analog calibration techniques needed to determine the changes (e.g., trimming) required. This can add cost to a resulting device, as well as complexity to the overall manufacturing process.
Other conventional approaches to addressing component variation can include large and/or complex analog circuits designed to accommodate anticipated variation in on-chip components. Such “over-designing” can also add to the cost and/or size of a resulting device, and can lead to lower yields when the device is fabricated.